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| White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY* 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED FEATURES DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V 0.2V JEDEC 184 pin DIMM package * JD3 PCB height: 30.48 (1.20") NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The W3EG6433S is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of sixteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR333@CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2 133MHz 2-3-3 DDR266 @CL=2.5 133MHz 2.5-3-3 November 2005 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 NC NC VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL NC A0 NC VSS NC BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DQM0 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DQM1 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 NC VSS DQ21 A11 DM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3 A3 D30 VSS DQ31 NC NC VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS NC A10 NC VCCQ NC VSS DQ36 DQ37 VCC DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DM5 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DQM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD A0-A11 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0, CK1, CK2 CK0#CK1#, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 NC W3EG6433S-D3 -JD3 PRELIMINARY PIN NAMES Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM No Connect November 2005 Rev. 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DM0 DM# CS# DQS DM# CS# DQS W3EG6433S-D3 -JD3 PRELIMINARY DQS4 DM4 DM# CS# DQS DM# CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DM# CS# DQS DM# CS# DQS DM# CS# DQS DM# CS# DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS6 DM6 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DM# CS# DQS DM# CS# DQS DM# CS# DQS DM# CS# DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DM# CS# DQS DM# CS# DQS DM# CS# DQS DM# CS# DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DDR SDRAMs VCCSPD SPD DDR SDRAMs VCC/VCCQ DDR SDRAMs DDR SDRAMs VREF VSS DDR SDRAMs DDR SDRAMs Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA R=120 CK0/1/2 CK0/1/2# Card Edge *DDR SDRAMs * DDR SDRAMs DDR SDRAMs DDR SDRAMs BA0 - BA1 A0 - A11 RAS# CAS# CKE0/1 WE# BA0-BA1 : DDR SDRAMs * Clock Wiring A0-A11 : DDR SDRAMs RAS# DDR SDRAMs : CAS# : DDR SDRAMs CKE : DDR SDRAMs WE# DDR SDRAMs : Clock Input DDR SDRAMs *CK0/CK0# 4 DDR SDRAMs *CK1/CK1# 6 DDR SDRAMs *CK2/CK2# 6 DDR SDRAMs *Clock Net Wiring Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown. 3. DQ, DQS, DM#/DQS# resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS#, CAS#, WE# resistors: 3 Ohms + 5%. November 2005 Rev. 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: W3EG6433S-D3 -JD3 PRELIMINARY Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 24 50 Units V V C W mA Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended perating conditions (Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Supply Voltage (for device with a nominal VCC of 2.5V) I/O Supply Voltage I/O Reference Voltage I/OTermination Voltage Input Logic High Voltage Input Logic Low Voltage Input Voltage Level, CK and CK# Inputs Input Differential Voltage, CK and CK# Inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver); VOUT = VTT = 0.84V Output High Current(Normal strengh driver); VOUT = VTT = 0.84V Output High Current(Half strengh driver); VOUT = VTT = 0.45V Output High Current(Half strengh driver); VOUT = VTT = 0.45V Symbol VCC VCCQ VREF VTT VIH VIL VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL VOH VOL Min 2.3 2.3 0.49*VCCQ VREF-0.04 VREF + 0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VCCQ VREF+0.04 VCCQ + 0.3 VREF -0.15 VCCQ + 0.3 VCCQ + 0.6 1.4 2 5 Unit V V V V V V V V uA uA uA uA uA uA 3 4 1 2 Note NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. November 2005 Rev. 2 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs CAPACITANCE TA = 25C. f = 1MHz, VCC = 2.5V Parameter Input Capacitance (A0-A11) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0, CKE1, CKE2) Input Capacitance (CLK0, CLK1, CLK2) Input Capacitance (CS0#, CS1#) Input Capacitance (DMO ~ DM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT W3EG6433S-D3 -JD3 PRELIMINARY Max 81 81 50 34 50 12 81 12 - Unit pF pF pF pF pF pF pF pF pF November 2005 Rev. 2 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS 0C TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V Includes DDR SDRAM component only DDR333@CL=2.5 Max 680 W3EG6433S-D3 -JD3 PRELIMINARY Parameter Operating Current Symbol IDD0 Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2 Max 640 DDR266@CL=2/2.5 Max 640 Units mA Operating Current IDD1 880 800 800 mA Precharge PowerDown Standby Current Idle Standby Current IDD2P 24 24 24 rnA IDD2F 200 180 180 mA Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 240 360 200 320 200 320 mA mA Operating Current IDD4R 1,120 960 960 mA Operating Current IDD4W 1,160 1,000 1,000 rnA Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 1,320 16 2,400 1,240 16 2,000 1,240 16 2,000 mA mA mA NOTES: * Module IDD was calculated on the basis of component IDD and can be different measured according to dq hearing cap. * IDD specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. November 2005 Rev. 2 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2.0 CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from Ck rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time (fast) Address and Control Input hold time (fast) Address and Control Input setup time (slow) Address and Control Input setup time (slow) Data-out high impedence time from CK/CK Data-out high impedence time from CK/CK Input Slew Rate (for input only pins) Input Slew Rate (for I/O pins) tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) -0.7 0.5 0.5 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTD tCCD tCK Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 +0.7 +0.7 -0.75 0.5 0.5 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K 335 (DDR333@CL=2.5) 262 (DDR266@CL=2.0) 263 (DDR266@CL=2.0) 265 (DDR266@CL=2.5) Max Min 60 75 45 15 15 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 Max Min 65 75 Max Min 65 75 Max Units ns ns Notes 120K 45 20 20 15 15 1 1 120K 45 20 20 15 15 1 1 120K ns ns ns ns ns tCK tCK 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 3 12 1.1 0.9 0.9 0.9 1.0 1.0 1.1 0.9 0.9 0.9 1.0 1.0 1.1 tCK ns ns ns ns i,5.7~9 i,5.7~9 i,6~9 i,6~9 1 1 +0.75 +0.75 -0.75 0.5 0.5 +0.75 +0.75 -0.75 0.5 0.5 +0.75 +0.75 ns ns V/ns V/ns November 2005 Rev. 2 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC Characteristics Parameter Output Slew Rate (x4,x8) Output Slew Rate Matching Ratio (rise to fall) Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refreash interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery & Precharge time Symbol tSL(O) tSLMR tMRD tDS tDH tIPW tDIPW tRDEX tXSRD tXSRD tREFI tQH tQH tQHS tWPST tRAP tXSNR 0.4 18 tWR/tCK + tRP/tCK) tHP-tQHS tCLmin or tchmin Min 1.0 0.67 12 0.5 0.45 2.2 1.75 6 75 200 15.6 - 335 (DDR333@CL=2.5) 262 (DDR266@CL=2.0) 263 (DDR266@CL=2.0) 265 (DDR266@CL=2.5) Max 4.5 1.5 Min 1.0 0.67 15 0.5 0.5 2.2 1.75 7.5 75 200 Max 4.5 1.5 Min 1.0 0.67 15 0.5 0.5 2.2 1.75 7.5 75 200 Max 4.5 1.5 Min 1.0 0.67 15 0.5 0.5 2.2 1.75 7.5 75 200 Max 4.5 1.5 Units V/ns ns ns ns ns ns ns ns ns tCK Notes j, k j, k 8 8 15.6 tHP-tQHS tCLmin or tchmin - 15.6 tHP-tQHS tCLmin or tchmin - 15.6 tHP-tQHS tCLmin or tchmin 0.75 0.4 20 tWR/tCK + tRP/tCK) 0.6 us ns ns ns tCK 4 11 10, 11 11 2 0.55 0.6 0.4 20 tWR/tCK + tRP/tCK) 0.75 0.6 0.4 20 tWR/tCK + tRP/tCK) 0.75 0.6 tCK 13 November 2005 Rev. 2 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Notes 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. For command/address input slew rate 1.0 V/ns. For command/address input slew rate 0.5 V/ns and > 1.0 V/ns For CK & CK# slew rate 1.0 V/ns. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 13. 11. 9. 10. W3EG6433S-D3 -JD3 PRELIMINARY Slew Rate is measured between VOH(ac) and VOL(ac). Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH. For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. tDQSQ Consists of data pin skew and output pattern effects and p-channel to n-channel variation of the output drivers for any given cycle. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266 at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks 2. 3. 4. 5. 6. 7. 8. 12. November 2005 Rev. 2 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR JD3 Part Number W3EG6433S335JD3 W3EG6433S263JD3 W3EG6433S263JD3 W3EG6433S265JD3 Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s CAS Latency 2.5 2 2 2.5 tRCD 3 2 3 3 W3EG6433S-D3 -JD3 PRELIMINARY tRP 3 2 3 3 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 2.54 (0.100) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2005 Rev. 2 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR D3 Part Number W3EG6433S335D3 W3EG6433S262D3 W3EG6433S263D3 W3EG6433S265D3 Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s CAS Latency 2.5 2 2 2.5 tRCD 3 2 3 3 W3EG6433S-D3 -JD3 PRELIMINARY tRP 3 2 3 3 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 30.48 (1.20) MAX 3.99 (0.157) (MIN) 2.54 (0.100) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2005 Rev. 2 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED W3EG6433S-D3 -JD3 PRELIMINARY Revision History Rev # Rev 1 History 1.1 Created Datasheet 1.2 Added lead-free and RoHS notes 1.3 Added AC specs 1.4 Moved from Advanced to Preliminary Release Date 12-04 Status Preliminary Rev 2 2.1 Added JEDEC standard PCB 2.2 D3 option is "NOT RECOMMENDED FOR NEW DESIGNS" 2.3 Added lead-free and RoHS notes 2.4 Added source control notes 2.5 Added industrial temperature options 5-05 Preliminary Rev 3 3.1 Update AC, IDD and cap specs 3.2 Add 333MH speed 11-05 Preliminary November 2005 Rev. 2 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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